Communication costs in a multi-tiered MPSoC

The amount of digital processing required for phased array beamformers is very large. It requires many parallel processors, which can be organized in a multi-tiered structure. Communication costs differ for each of the stages in such an architecture. For example, communication costs from the antenna front-end to the first processing stages is costly because of the amount of connections and data rate. Furthermore there is a trade-off between sequential processing exploiting locality of reference versus exploiting parallelism but adding communication costs. Thus, the optimal architecture depends on the importance that is given to the different measures.\ud \ud A model is presented to determine the partitioning of a (beamforming) system based on communication costs. It is shown that different solutions can be explored based on the cost model and the incorporated quantitative and qualitative measures. Determining the importance of each measure is subjective to the situation and application. In this work a simple beamforming application is used optimised for energy efficiency

Angular CMA: A modified Constant Modulus Algorithm providing steering angle updates

Conventional blind beamforming algorithms have no direct notion of the physical Direction of Arrival angle of an impinging signal. These blind adaptive algorithms operate by adjusting the complex steering vector in the case of changing signal conditions and directions. This paper presents Angular CMA, a blind beamforming method that calculates steering angle updates (instead of weight vector updates) to keep track of the desired signal. Angular CMA and its respective steering angle updates are particularly useful in the context of mixed-signal hierarchical arrays as means to find and distribute steering parameters. Simulations of Angular CMA show promising convergence behaviour, while having a lower complexity than alternative methods (e.g., MUSIC)

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

DVB-S Signal Tracking Techniques for Mobile Phased Arrays

Abstract—A system that uses adaptive beamforming techniques for mobile Digital Video Broadcasting Satellite (DVB-S) reception is proposed in this paper. The purpose is to enable DVB-S reception in moving vehicles. Phased arrays are able to electronically track the desired signal during dynamic behaviour of the vehicle the array is mounted on.\ud The proposed system uses blind beamforming to adapt the array steering vector to changing signal (conditions and) directions. Movement of the vehicle, the phased array is mounted on, leads to modulus and phase deviations at the beamformer output. An extended version of the Constant Modulus Algorithm (CMA) algorithm is used to adapt the steering vector weights to compensate for those deviations.\ud For simulation of the proposed system a model of vehicle dynamics is used to generate realistic antenna data. Simulation of the proposed system based on this antenna data shows appropriate corrections for modulus and phase deviations

Fundamentals of Geomorphology, 3rd edition

Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation

Efficient architectures for streaming applications

This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept will not only be applied on chip level but also on board-level and system-level. The tile concept has a number of advantages: (1) depending on the requirements more or less tiles can be switched on/off, (2) the tile structure fits well to future IC process technologies, more tiles will be available in advanced process technologies, but the complexity per tile stays the same, (3) the tile concept is fault tolerant, faulty tiles can be discarded and (4) tiles can be configured in parallel. Because processing and memory is combined in the tiles, tasks can be executed efficiently on tiles (locality of reference). There are a number of application domains that can be considered as streaming DSP applications: for example wireless baseband processing (for HiperLAN/2, WiMax, DAB, DRM, DVB), multimedia processing (e.g. MPEG, MP3 coding/decoding), medical image processing, color image processing, sensor processing (e.g. remote surveillance cameras) and phased array radar systems. In this presentation the key characteristics of streaming DSP applications are highlighted, and the characteristics of the processing architectures to efficiently support these types of applications are addressed

Efficient Architectures for Streaming DSP Applications

Abstract — In this paper we focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept has a number of advantages: (1) depending on the requirements more or less tiles can be switched on/off, (2) the tile structure fits well to future IC process technologies, more tiles will be available in advanced process technologies, but the complexity per tile stays the same, (3) the tile concept is fault tolerant, faulty tiles can be discarded and (4) tiles can be configured in parallel. Because processing and memory is combined in the tiles, tasks can be executed efficiently (locality of reference). There are a number of application domains that can be considered as streaming DSP applications, for example wireless baseband processing (for HiperLAN/2, WiMax, DAB, DRM, and DVB), multimedia processing (e.g. MPEG, MP3 coding/decoding), medical image processing, color image processing, sensor processing (e.g. remote surveillance cameras) and phased array radar systems. In this paper the key characteristics of streaming DSP applications are highlighted, and the characteristics of the processing architectures to efficiently support these types of applications are addressed.